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rusefi-sti-2004

Plug-and-play rusEFI ECU for the 2004 Subaru Impreza WRX STI (USDM, GD chassis, EJ257). Repo angelEmbeddedEra/rusefi-sti-2004 (public fork of rusefi/hellen-example), clone at ~/rusefi-sti-2004, submodules hellen-one and kicad6-libraries (git submodule update --init). Board rusefiSTI2004 rev a (rev b on branch rev-b-schematic-fixes). Related: KiCad.

Built from Hellen-One modules: mega-mcu144 0.7, power 12/5V, 2x VR discrete, 2x knock, 2x motor driver (ETB), WBO, CAN, AUIPS2041L low-side drivers, TE 1-1376430-0 135-pin connector. Car documents (OEM ECU pinout, wiring PDFs) in documents/.

Open

  • Layout v2: bigger, gridded, symmetric board (owner decisions 2026-10-17: outline 170 x 130 mm, ALL numbers round, no decimals (SOP-021 1.18); try 4 layers again (In1 GND, In2 +12V_RAW, signals F/B) and fall back to 6 only if the bench says so; swap WBO to 0.6 and use the newest of every module/part). Started 2026-10-17 on branch layout-v2: WBO swap + latest audit, and a read-only floorplan scorer, with workers. Today 144.6 x 113.6 mm, 6 layers, 130 parts, M1 2.15 mm from the right edge with 34 signals on that side. Enclosure is printed afterwards (SOP-024), so the outline is free. Plan on a branch layout-v2 (current board stays): (0) finish the schematic first: merge rev-b-schematic-fixes, decide wbo 0.5 -> 0.6 (changes the module footprint), Update PCB; (1) read-only scorer on a board copy (HPWL, ratsnest crossings, tracks demanded vs available across cut lines) to get a baseline number for today's board, trying KiCadRoutingTools place_optimize (MIT) first per kicad-autorouter auto-placement idea; (2) get the real max envelope in the car (owner) and pick outline, recommended about 170 x 130 mm (+35% area), try 160 x 125 and a grid-snapped 144.6 x 113.6 as controls; (3) grid: modules, connectors and drivers on 1.0 mm origins, passives 0.5 mm, rotations 0/90 only, repeated driver banks at one pitch, mounting holes and outline on 5 mm; (4) floorplan by signal flow: J1 left edge, output drivers beside their J1 pin groups, inputs band, power top, M1 centre with 5+ mm free on every side, analog (VR, knock, WBO) in a quiet corner away from the drivers and motor driver, USB-C and CAN on the far edge, mirror-symmetric where parts repeat; (5) write it into pcb_place.json, kicad-pcb-from-netlist, route with the same stage order and grade each variant with the eeroute bench (opens, DRC, bends, share of length at class width). Honest limits: size does not fix the J1 pin field (2.61 mm pitch, only 0.8 mm tracks pass, so the ETB necks stay unless the drivers sit right at J1) or the interleaved USB-C pad order (needs a via); cost rises with area; 6 layers stay.

  • Route the board by documents/ROUTING-PLAN.md (rusefi-sti-2004 repo): 10 stages, commit + push after each, gate DRC 0 errors / parity 0. Stage 0 first: confirm the enclosure for H1-H4, set the JLC04161H-7628 stackup, lock connectors and modules.

  • Order the drivers not stocked at JLC and consign them: 10 x VNLD5160TR-E (SO-8; LCSC C377942 is at 0) and 1 x NCV8401BDTRKG per board, Digi-Key/Mouser. Bench-check one VNLD channel driven from the 3.3 V MCU output (ST specifies the input threshold as 1-3.5 V) before trusting all 19.
  • Library branch sti2004-parts (kicad-lib, 452a71d, pushed): owner is adding the STEP models for TE_1-1376430-0 and the Mini-Fit Jr 2x07. Then pull, kicad-check clean, merge to master (pre-push gate), kicad-erp-sync audit / pull dry-run / --yes per SOP-008, install-kicad-libs.sh.
  • Still open from the completeness review: EVAP C12/C21/A24 if ever needed; SD-card logging module and status LEDs as options. Order the J3 mating plug (Molex 39-01-2140 + 39-00-0038 terminals).
  • LSU 4.9 adapter pigtail for front plug B18 (table in documents/README.md): before relying on it, confirm the A25 shield is not grounded at the sensor end (it carries Ip) and whether the rusEFI WBO firmware needs Rtrim (pad P4 only).
  • Module check 2026-10-17 (vs rusefi/hellen-one, hellen154hyundai, uaefi): M3 wbo is 0.5, upstream is 0.6 (2026-03-22, used by the newest uaefi). 0.5 carries a through-hole VNP28N04-E TO-220 (Q601, no LCSC number: hand-soldered or consigned, against our all-SMD one-reflow plan); 0.6 drops it for a SOT-223 VNN7NV04P (LCSC C501115), 3 mm shorter, one pad fewer. Symbol change: pins LSU_H+/LSU_H- become one LSU_Htr (heater return), so the heater wiring on the Comms sheet changes (today: H- to GND, H+ switched return). Decide with the owner, then swap footprint + wiring before routing. All other modules are current or the only version: mega-mcu144 0.7 (hyundai uses 0.6), motor-driver 0.1, vr-discrete 0.5, power_12and5V 0.3, knock 0.2, lin 0.1, dinput4 0.1.
  • Firmware: K-line on UART8 (M10 LIN module); cruise buttons IN_D1/3/4 and lamps OUT_IO5/6 have no native rusEFI cruise, plan Lua; WBO over CAN.
  • Firmware config (rusEFI): use the M1 pin map in documents/README.md (cams IN_CAM / IN_AUX1 as Hall with pull-up; AVCS OUT_PWM4/5 ~300 Hz; wastegate OUT_PWM1 15-30 Hz; FPCU command IGN5 5 V PWM, 0 V = pump off). Verify the cam pattern (Haltech/MoTeC: 4-1 on the intake cams) and crank 36-2-2-2 offset with the trigger logger.
  • On the car: scope the stock ECM's B26 fuel pump command (carrier frequency unknown) before removing it; if the tach is dead, add 1-4.7k pull-up to 12 V on A23.
  • Before first power-up, meter on the car: D14/D15 and B26/B27 (rusEFI's 2005 Mitchell pinout swaps each pair vs the FSM), A22 (wired to charging CHG-01, function unknown), ETB motor polarity D4/D5.
  • Review and merge rev-b-schematic-fixes (71f140f, 2026-10-13): fixes IGN3/4 shorted to IGN1, ETB PWM/DIR/DIS order, INJ7/INJ8 both on fan relay 2, second VR paralleled on crank (now LH cam), floating sensor 5V, VSS not connected. Then "Update PCB from Schematic" and re-route.
  • Licence: andreika-git/hellen-one and rusefi/kicad6-libraries declare no licence on GitHub (rusefi/rusefi is GPL). Settle what may be built and sold before this becomes an EmbeddedEra product.
  • Library rule: the design uses hellen-one / rusEFI libraries and KiCad stock power:, not the EmbeddedEra library (kicad-own-libraries-only). Decide whether that rule covers this board.

Log

  • 2026-10-19: Physical45°/heading-aware native planner completed (eeroutea313855; library215f8b5; fork unchanged).145Python/43editor checks, stock/full fixture audit and saved visual review pass. Three new bounded STI corridors retain no copper: C1/R43 shoves create invalid branch angles; M1 head stops. Original PCB/project/rules byte-exact at115opens; current implementation/evidence and next native-shove work in kicad-autorouter.
  • 2026-10-19: Native waypoint diagnosis on disposable copies reproduces C1/R43 short arrivals and M1 fixed90° join; dropping M1 prior checkpoint rescues only its prefix, next checkpoint remains blocked. No real Apply/Save/promotion, original PCB/project/rule bytes exact at115opens.39editor/66Python checks; source heads/evidence/next work in kicad-autorouter.
  • 2026-10-19: Automatic native target-copper planning added (eeroute996f090; fork05bf3ed8 unchanged). Fixture track/via completions pass saved stock/full-report gates; real M1:N32 rail trial reaches existing copper and reduces115→114opens but adds one forbidden45° branch join (two DRC records), so candidate rejected and source remains115opens with exact original PCB/project/rules. Native history/partition checks pass;125 Python tests. Next: native multi-arm angle guard and a legal retained connection; full current handoff/evidence in kicad-autorouter.
  • 2026-10-19: Native reference association completed and verified on disposable STI copies (fork05bf3ed8/eeroute096062b). Three R40 moves retain115opens/six bends/teardrop gates with zero new complete-report findings under byte-exact original project/rules. R53±1mm reject because no associated clear reference fits the existing4mm bound; old R53 label independently measures nearer R52.311 native editor checks,112 Python tests and ten integer boundary controls pass. Original PCB/pro/rules hashes unchanged; no candidate promoted. Current tool handoff and next copper-target planning step: kicad-autorouter.
  • 2026-10-19: Continued the newer native-tool handoff linked from this note. Six apparent new M1 silk partners were stock10.0.7 capped-report selection changes (199reported vs502complete), with M1 unchanged. Four R40/R53 saved placement copies have zero new complete-fork findings,115real opens, six bends and passing teardrop gates; original STI board/project/rules hashes remain exact and no candidate was promoted. Audit now rejects incomplete all-finding proof and records full diagnostics separately;112 Python tests pass. Tool branch native-complete-drc-audit8a0b7d7; details and next reference-association work in kicad-autorouter.

  • 2026-10-18: Native KiCad PNS USB_D+ U1:6→M1:N3 routed on separate layout-v2-native-usb-breakout branch268b447, worktree ~/eeroute/work/route_H_native_usb. Ordinary stock KiCad10 PCB, saved refill/stock10.0.7 check: target1→0open, real board116→115, one new via outside modules, VBAT shoved outward,0new findings/regressions, house bends6→6, teardrop gate passes. All130placements/950pad geometries/nets unchanged; project/rules exact. Eight baseline errors and unfinished USB_D−/pair matching/impedance/return-path gates remain. Original route_H c0ed69a and layout-v2 worktrees untouched. Full checkpoint in this branch’s documents/ROUTING-PLAN.md; tool proof in kicad-autorouter.

  • 2026-10-13: Cloned and reviewed. KiCad 8 files (open fine in 10.0.7). ERC master 315 errors / rev-b 308 (mostly unconnected module pins: 212 pin_not_connected, 90 pin_not_driven); DRC master 337 unconnected items (layout barely started, last real layout commit 2025-02-19), 4 clearance, 4 drill-out-of-range.

  • 2026-10-13: Pinout cross-check built: documents/oem-ecm-pinout-2004-sti.csv (135 terminals from FSM EN(STi)-18..22 + WI-106/107), tools/pinout_check.py -> documents/STI2004-pinout-check.xlsx (GridCraft) + findings .docx (WordCraft). rev-b: 47 OK, 3 mismatch, 16 label only, 34 not wired. FSM misprints: IG#4 is B15 (table says B16), A/C relay is B135 33 (table says B133 33). Footprint lib was G:/My Drive/... -> ${KIPRJMOD}/STI.pretty. Docs moved to documents/fsm/, lock file/autosave/stale gerber/ removed.

  • 2026-10-13: Independent check (Fable, read-only) rebuilt all 135 terminals from the FSM: 134/135 agree. Fixed: A22 wired to charging (WI-111), A/F is Denso 4-wire (WI-113), D29 to DLC pin 6 (WI-112). Model year consistent with 2004 USDM STI (I/O table PDF dated 2003-05-12; rusEFI files the identical table as 2005-07). allpinouts.org 2004 STI page is a 2002-03 WRX layout: ignore.

  • 2026-10-13: rev-b-wiring: fixed MAF/MAP swap, D7/A34 to GND, stray D22, clutch rename; cams are 3-wire Hall (WI-114) so M6 VR module taken off; wired switches (4.7k pull-downs for 12 V-active), analogs, FPCU B26 from IGN5, +2 INJ4 low-side sheets (Q9-16) for WG/AVCS/purge/MIL/rear heater/A-C/tach, AVCS (+) to +12V_RAW, TGVs on M9 in parallel. Net-checked; ERC 308->235 errors; pinout check 78 OK. Research by Sonnet (Hellen I/O) and Fable (car wiring) agents, read-only.

  • 2026-10-13: Owner: front O2 = Bosch LSU 4.9 (WBO module M3, via stock harness A33/A26/A25 + JP1-3, pads for a pigtail); K-line via LIN module; cruise wired (LS4 for lamps). Owner rule: every uncertain circuit gets an option footprint (DNP + bom_replace line), see pcb-option-footprints. 12 DNP options, pads for spares, proto area. Pinout check 94 OK. Commit e3c54b7.

  • 2026-10-13: Completeness review found 3 blockers, fixed in 8259556: M1 GND_G unconnected, F5 50 mA PTC in the ETB motor supply, no USB. Added USB mini-B + BOOT0/SWD pads, two dinput4 modules (D11-D14, D24, 3 aux inputs), removed M6/M4. I2C expander rejected: no rusEFI driver; MC33972 obsolete. Pinout check 99 OK.

  • 2026-10-13: Pedal C15 on its own 5 V (M8 5VP), CAN terminator option R52 (M1 already has 120R internally, WBO none), aux connector J3 Molex Mini-Fit Jr 2x7 (pinout in documents/README.md). Pinout check 99 OK, ERC 148 errors (from 308).

  • 2026-10-13: Schematic split into 8 functional sheets + overview with a note on each (Connector, Power, Mcu, Sensors, Inputs, Outputs with nested LS sheets, Comms, Aux); net names and connectivity identical to the flat design (KiCad 10 and 8.0.7). 0 text overlaps enforced by ~/.local/bin/kicad-overlap-check. USB is now USB-C (HRO TYPE-C-31-M-12 + USBLC6-2SC6). Imported KiCad 10 library symbols/footprints need converting for KiCad 8 (hide flags, embedded_fonts etc.). Option table generated by tools/options_table.py. SOP-021 1.5.

  • 2026-10-13: Owner: use EmbeddedEra libraries and the template; Hellen-One modules are the one exception (decision note updated). All other symbols swapped to EmbeddedEra parts (new ones on kicad-lib branch sti2004-parts), template applied (worksheet, net classes, JLCPCB rules, text vars, net names), board migrated to KiCad 10. Connectivity identical, 0 overlaps (checker now also catches overlapping bodies and fields on wires).

  • 2026-10-13: Board package builds on our machine: tools/create-board.sh (Hellen export in kicad/kicad:10.0.5, then the hellen-one docker steps). hellen-one submodule bumped to upstream master, which is KiCad 10 native (refill zones in-memory, kicad-cli VRML). All GitHub workflows removed (kicad-checks-on-server). bom_replace renamed to rev b. rev-b-wiring fast-forwarded into master (b574ebe).

  • 2026-10-13: Sheets tidied to owner style (GND down, rails up, vertical pulls, KiCad-autoplaced fields) by tools/sch_tidy.py; netlist identical. M7 removed (one knock sensor). Overlap checker fixed: KiCad flips field justification for some angle/rotation/mirror combos, and power arrows count as bodies; it had been missing 28 overlaps. F1-F4 moved to a spaced block (IGNn_COIL labels). 6232a1b.
  • 2026-10-13: NCV8401BDTRKG recommended to replace VND14NV04 (same DPAK pinout, 28 mOhm, 25-35 A limit, AEC-Q101, Digi-Key 22k stock); not on LCSC/JLC. Awaiting owner OK.
  • 2026-10-13: Parts audit: every symbol and footprint exists (the 210 ERC not-found warnings are the sti2004-parts branch, not merged yet). Fixed U1 (was the USBLC6-2P6 symbol hand-edited to SOT-23-6; now EmbeddedEra:USBLC6-2SC6, EE-C-0146), J2 MPN/Mfr, P1-P32/G1 out of the BOM. Generic passives have no IPN by design (SOP-008 s7); Panasonic 1206 LCSC blank by design. ae0b5e5.
  • 2026-10-13: Owner approved: Q1-Q20 VND14NV04-E -> onsemi NCV8401BDTRKG (same DPAK pinout/footprint, protected, AEC-Q101). Library symbol on sti2004-parts (c28a8a9); board 293ad8d, netlist unchanged.
  • 2026-10-13: Board tools moved to the KiCad library repo for reuse (kicad-tidy-check, kicad-overlap-check, hellen-create-board); board repo d559da7. Reusable facts went to protected-low-side-drivers, subaru-ecm-connectors, usblc6-2.
  • 2026-10-13: PCB rebuilt from the schematic headless (kicad-pcb-from-netlist, new in EmbeddedEra/KiCad scripting/pcb): 137 footprints, DRC schematic parity 0, no courtyard overlaps; floorplan in pcb_place.json. H1-H4 mounting holes added (schematic first). STI.pretty removed. hellen-create-board completes again.
  • 2026-10-13: Net classes fixed before routing: GND -> Ground (was Default 0.2 mm), +12V_RAW/+12V_ETB/OUT_ETB -> Power_5A 2.5 mm, OUT_TGV -> Power_3A; template gained the same classes.
  • 2026-10-13: Decided 4 layers (Hellen modules carry In1/In2; Hellen build default) with In1 GND plane, all parts top-side (one stencil/reflow). Placement spaced for routing, silk references JLC-size and overlap-free. Found: a bad (constraint ...) line makes KiCad ignore the whole .kicad_dru silently; Board Setup minimums are floors custom rules cannot go below.
  • 2026-10-13: Planes laid: In1 GND, In2 +12V_RAW, outer GND pours + stitching, DPAK drain spreaders with thermal vias; DRC 0 errors, 326 unconnected left to route. J1 inner pad rings trimmed so planes reach its pins (2.61 mm pitch, 2.0 mm pads).
  • 2026-10-13: Drivers sized per load (owner): 8 NCV8401B DPAK, 4 ZXMS6006DGQ SOT-223, 8 ZXMS6004FF SOT-23F (821caab); purge/O2 heater and spares regrouped, every output keeps its J1 and MCU pin. Library 82cd70a.
  • 2026-10-13: Owner: follow the newest rusEFI boards. Outputs now 10 x VNLD5160 dual SO-8 + 1 NCV8401B DPAK (rear O2 heater), 45d70aa; every output kept its J1/MCU pin. Compared all other functions with uaefi-f / hellen-112-17 / hellen154-e: our Hellen modules already carry the same ICs (F767, LMR14020+TLS115, TLE9201SG, rusEFI WBO, LMV321, TJA1021, TJA1051). See protected-low-side-drivers.
  • 2026-10-13: Passives placed next to the pin they serve (kicad-pcb-from-netlist anchored placement): gate pull-downs at driver inputs, input pulls beside J1, CC resistors at J2, fuses at their connector.
  • 2026-10-13: Routing plan written (documents/ROUTING-PLAN.md); SOP-021 1.10 carries the generic routing order.
  • 2026-10-13: Stage 2 (ETB, TGV, WBO heater, rear O2 heater) routed headless with kicad-autoroute; DRC 0 errors, unconnected 320. Hellen modules carry long thin outline-strip pads, so ignore pads with aspect > 3 when finding edge pins; route a net first when its pin opens into a channel other nets would fill (WBO_HEATER E5 into the 3 mm M3/M2 gap).
  • 2026-10-14: Added on-board MAP sensor copied from AlphaX-4chan: U20 MPXHZ6400AC6T1 (LCSC C511770, axial top port) + 100 nF on +5VA -> M1 IN_MAP3 (S19), as rusEFI's on-board MAP channel. TGV RH moved to IN_RES2 (S14); J3 pin 8 is now NC; external MAP stays on IN_MAP1. The lid needs a hose hole above U20.
  • 2026-10-14: Owner rule: move parts, not traces, when a track has to neck down (SOP-021 1.12). Stage 2 rerouted: the first pass had left OUT_ETB+ and OUT_TGV_OPEN unrouted; now all 7 routed at 0.8 mm then widened (ETB about half at 2.5 mm, the rest necks in the J1 pin field), 8 parts nudged, U20 moved out of the ETB corridor to the gap east of M2. New tool kicad-nudge. Found: .kicad_dru lengths without mm disable the whole file.
  • 2026-10-14: Enclosure will be 3D printed around the board (SOP-024), so the board sets hole positions (H1-H4 stay) and the lid gets a hose hole above U20. Stackup JLC04161H-7628 set (kicad-stackup, community generator, order FR-4 TG155); anchors locked. ETB necks doubled on the other layer where a tie-back via fits (27 mm).
  • 2026-10-14: Teardrops are headless after all: kicad-cli pcb drc --refill-zones --save-board writes them (166 pad/via teardrops); the earlier 'GUI only' finding was a bad grep ((teardrop and (type padvia) are on separate lines). Found and fixed: KiCad's ImportSpecctraSES replaces ALL routing, so commit ef3e072 had lost stage 2 and the fan-out; restored in 2d46ece, and kicad-autoroute now keeps other nets' copper and fails on any per-net regression. Driver inputs 15/20 routed; the rest are blocked because M1 sits 2.15 mm from the right edge with 34 signals on that side.
  • 2026-10-15: Board went to 6 layers (owner): In3 signals, In4 GND, JLC06161H-7628; In3/In4 keep clear only of the Hellen modules' own vias (802, located from each module's drill file); hellen-create-board patched for 6 layers (Sonnet worker, verified). Routing at 24 open connections, DRC 0 (commit def43ad); several router/import bugs found and fixed in kicad-lib (see scripting/README Known traps).

  • 2026-10-16: The open count was understated: kicad-lib opens.py dropped every unconnected pair with one Hellen module pad, so passive-to-module opens (e.g. R31 pad 1 to M1 S7) were hidden. Fixed (kicad-lib 9c56088, test_opens.py). At def43ad: 49 real open connections, not 24/26. Newly visible: NRST, SWDIO, SWCLK, BOOT0 x2, I2C_1_SCL/SDA, OUT_IGN1-4, SPARE_IGN6-8, SPARE_PWM3, FP_CMD, IN_CRUISE_SET, IN_PS_PRESSURE_SWITCH, IN_BLOWBY, IN_TEST_MODE, plus a second open on AUX_AN2, IN_VMAIN, IN_DEFOG. Found by the eeroute bench.

  • 2026-10-17: rusEFI check of the mega-mcu144 module (read-only, from GitHub): module 0.7 = STM32F767ZI LQFP144 (F7 2MB is the stated default, H7 explicitly unsupported), same module as rusefi/hellen154hyundai_f7 (board.mk includes hellen-common-mega144.mk; pad names -> H144_* in rusefi firmware/config/boards/hellen_meta.h). The generic rusefi/fw-custom-mega144-f7 is an Arduino-style breakout (M144_D0..53/A0..15), NOT the ECU pin names: do not use it for this board. Firmware path = own fw-custom-* repo from rusefi/fw-custom-example with a connectors YAML J1 pin -> H144_*, modelled on hellen154hyundai_f7. Upstream module changes since 0.7: 2026-03-27 BOM swaps U103 SN74LVC4245A -> SN74LXCH8T245 (our submodule is at master 2026-10-13, so it has it); issue 378 notes ~50 mA per IGN output (fine for logic-level igniters, verify the STI coil igniter input before relying on it); PPS2 has a repair guide (hellen-one modules/mega-mcu144/PPS2.png); IN_AUX3 analog works only if R131 is populated. Data copies in ~/eeroute/research/data/.

  • 2026-10-17: layout-v2 branch started (board repo 5dcc436): WBO M3 swapped 0.5→0.6, heater is now one pin LSU_Htr (E5→WBO_HEATER, E6/GND removed; evidence: hellen-one 0.6 schematic p1 + uaefi M5), ERC 371→370, overlaps 0, netlist diff = only GND loses M3.E6. All other Hellen modules already newest. Audit finding: J1 TE 1-1376430-0 is OBSOLETE (Digi-Key and Mouser stock 0). Candidate 1-1376430-8 (same TE drawing 1376430, Active, DK 1074 @ $15.30) — drop-in for the footprint UNVERIFIED, check the TE drawing before the new floorplan commits to J1. PCB still holds the 0.5 footprint until kicad-pcb-from-netlist is rerun.
  • 2026-10-17: floorplan scorer ready (see kicad-autorouter note); floorplan v2 (170×130, 4 layers, round numbers) delegated, compare variants by scorer table. Brief: ~/eeroute/work/briefs/floorplan_v2.md.
  • 2026-10-17: owner: "I have j1" — J1 (TE 1-1376430-0) is in hand, so the obsolete listing does not block this board; keep the current J1 footprint (no -8 swap). Still worth a note for any production run beyond the stock on hand.
  • 2026-10-17: layout-v2 floorplan A (board repo da9852c, 130×170 portrait, 4 layers, 0/130 origins off whole mm, WBO 0.6 in the bottom-left corner, DRC clean of courtyard/hole/edge). Made by a simulated-annealing optimiser (~2h50m). My re-run of the scorer: at the 4-layer model (--layers 2) overload 56.4→35.5 tracks, crossings 3701→2084, HPWL 14560→11850 vs the current 6-layer board; at the 6-layer model A is WORSE (2.3→17.5). Defects: drivers U10-U19/Q16 sit far from the J1 pins they drive, M14 power module is not near J1's power pins, J1 face direction unverified. Not accepted yet. Two follow-ups running: (1) real routing trial of A in worktree ~/eeroute/work/route_A (branch layout-v2-routeA), (2) hand-zoned plan H with drivers beside J1 (branch layout-v2-H). Decide by routed result, not the scorer alone. Lesson: the scorer under-reports overload (model 3.9 vs real 35.5), the optimiser tuned toward it and broke signal-flow rules; hand zoning first, scorer second.
  • 2026-10-17: hand-zoned plan H (branch layout-v2-H cf24827, best H1a: J1 right long edge, M1 rot 90, drivers in one column 14-21 mm from their J1 pins, M14 24 mm from +12V_IGN but 60 mm from the +12V_RAW pads, symmetry partial). Scorer at 4 layers: overload 255 tracks / 29 cuts vs A's 35.5 / 10, though HPWL 10311 and crossings 1610 beat A (11850 / 2084). Hot spots near M14/M8 (sheet x150-175 y50-70) and between M1 and the driver bank. Hand variants all worse than A on overload (H1 295, H1b 307). Waiting on the routed trial of A to say whether overload numbers mean anything.
  • 2026-10-17: routing trial of floorplan A (branch layout-v2-routeA, worktree ~/eeroute/work/route_A, 4 layers, existing tools, Freerouting optimizer OFF because it hung 20 min): start 277 real opens → s1 plane fan-out 274 → s2 high-current 263 → s3a drains 239 → s3b driver inputs 200 (6 DRC errors: tiny stubs, one via clearance, one edge clearance). Drivers/J1 stages gave no regressions. Full board not routed; the M1-bound/analog stages (the squeeze question) come next. Resumed worker on A (75 min) + new worker routing H1a the same way on layout-v2-routeH (90 min); compare stage tables. 6 nudged parts in A broke whole-mm (re-snap later).
  • 2026-10-17: route A continued (layout-v2-routeA e818b43): s4 analog 200→157 opens (7 DRC errors; 6 analog nets failed: IN_KNOCK_RAW, THRESHOLD_VR_CR, IN_TUMBLE_SENSOR_RH, IN_FUEL_LEVEL, IN_TPS_MAIN, IN_PPS_MAIN, along the west side J1↔M1); s5 inputs/switches/aux (47 nets) and s5a hit Freerouting's time limit twice and wrote nothing (machine was loaded by the parallel H1a run); s6 rails/CAN/USB/K-line 157→123 opens, 9 DRC errors. 96% of routed length is at class width. Opens left: Default 42, Signal_Robust 63, Power_500mA 13, Power_1A 3, USB2 2. Not a clean verdict on 4 layers: no router refusal seen, only timeouts; the 41 input nets and ignition nets were never run. For reference the 6-layer board reached 24 opens after much more effort. Teardrop state after s6 unverified.
  • 2026-10-17: route H1a on 4 layers (layout-v2-routeH c0ed69a, Freerouting, optimizer off): through s3b within 1 open of A at every stage (276→273→262→238→199); s4 analog 156; s5+s6 rails/CAN/USB/K-line 116 real opens, 7 DRC errors (5 new clearance errors from +5VA near IN_MAP_ONBOARD and near IN_CRANK+, committed unclean). Remaining opens: 60 of 116 end at M1, 38 at J1, clusters at (100,100) debug/ETB, (160,40)/(180,60) J1-side switch inputs, (120,120) ignition. 13 analog nets left with 1 open each. Cause not tested; M1 pin-field congestion with only F/B for signals is the leading suspect (In2 unused). Floorplan choice: A and H1a route equally at these stages, so H1a is preferred because it meets the signal-flow rules (drivers beside J1). Next: same plan on 6 layers (layout-v2-routeH6, worker running, machine otherwise idle) for a like-for-like 4-vs-6 measurement.
  • 2026-10-17: H1a on 6 layers (layout-v2-routeH6 debfb23, In3 signal + In4 GND, optimizer off from s3a): real opens 4-layer vs 6-layer: s2 262/262, s3a 238/239, s3b 199/201, s4 156/147. In3 carried 2706 mm at s4 (half of all copper) yet only 9 fewer opens. Opens ending at M1/J1 at s4: 66/40 on 4 layers, 57/35 on 6. So a third signal layer does NOT clear the M1 pin-field congestion; it is placement/escape, not layer count. s56 and later stages not run on 6 layers (s4 alone took 25 min). Two new DRC errors (FAN_RELAY_2 In3 track in a module-via keepout; IN_FUEL_LEVEL via vs IN_CAM In3 track), unfixed. The worker patched module_vias.py locally (rotated-module keepouts; 6 of 11 modules rotated, incl. M1): route_H6_snap/module_vias_rot.py, worth upstreaming to the kicad-lib tool. Next: look at M1 escape (clearance around M1, pin-field fan-out) before spending more routing time.

  • 2026-10-18 HANDOFF (layout v2, new chat starts here): nothing is running. Branches in ~/rusefi-sti-2004: layout-v2 (WBO 0.6 + floorplan A, 130x170), layout-v2-H (plan H1a, preferred: drivers beside J1), layout-v2-routeA, layout-v2-routeH (4-layer, 116 real opens after s5+s6, 7 DRC), layout-v2-routeH6 (6-layer, 147 at s4 vs 156; third layer does not fix M1). Worktrees and stage snapshots in ~/eeroute/work/route_{A,H,H6}[_snap]; stage order, net lists and ar_noopt.sh are in route_H_snap. NEXT (not started): diagnose M1 escape on H1a (M1 ends 60 of 116 opens; check M1 clearance, test pads/jumpers too close, escape fan-out), adjust placement, re-snap parts to whole mm, then re-run only the unrouted stages (inputs/switches/aux/ignition/leftovers) on 4 layers, one Freerouting job at a time. Also open: owner's real enclosure envelope (130x170 assumed), owner's "couple other things" (never said), upstream module_vias_rot.py to kicad-lib, clean DRC (+5VA clearance x5, stubs), verify teardrops, no GitLab push until owner says.

  • 2026-10-18: Codex readback verified all five layout worktrees clean at the handoff heads (A da9852c, H cf24827, routeA e818b43, routeH c0ed69a, routeH6 debfb23); no router/build jobs observed. Fresh stock KiCad 10.0.7 DRC on a temporary copy of routeH, with original project/rules, refill, severity-all and all-track-errors: 116 filtered real opens / 185 raw, 8 routing errors (6 clearance, 2 track_width), 98 track_angle warnings; 674 teardrops. The saved stage report lists 7 errors (5 clearance, 2 width); the fresh command exposes one additional clearance record. Source board/project/rules hashes unchanged. H1a remains the preferred experiment; next is M1 escape diagnosis, then the unattempted input/ignition/leftover stages, one heavy job at a time. Earlier 24-open claims refer to the old counting bug (49 corrected), not a finished board.

  • 2026-10-18: Related autorouter execution fixes completed and verified; see kicad-autorouter current handoff. Board/layout files and worktrees remain unchanged. The router’s 7-open result is a seven-net historical-stage benchmark, not a new open count for the H1a layout (still the 116-open handoff).

  • 2026-10-18: eeroute checkpoint bd694c1c/9a0a978 adds ground repair and declared USB/CAN breakouts; see kicad-autorouter current handoff. Historical-stage benchmark copies only: USB8→4, CAN8→6, seven-net replay11→3, zero new findings/regressions; no full completion. All board worktrees unchanged/clean; H1a routeH c0ed69a still116 real opens.

  • 2026-10-18: Native-workflow continuation: KiCad fork6d534a54/eeroute4bae4f3 verify actual GUI IPC editing/undo and reduce redundant GND stitch retries. Fresh historical-stage seven-net replay still3opens,0new findings/regressions. Production/STI worktrees unchanged; see kicad-autorouter current handoff for full native AI goal and next session API.

  • 2026-10-18: Read-only VectorCraft planning view generated from H1a c0ed69a,130footprints, original board/project/rules hashes unchanged. Private NAS artifacts at design/pcb-planning/sti-h1a-20261018/final-verified/; editable review boxes and heuristic pressure overlay only. No placements/routes applied; see kicad-autorouter current handoff.