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Switched_USB_Hub

1 upstream / 4 downstream USB hubs whose ports the host PC switches on/off (power + data), no firmware. Two boards in one repo: USB 2.0 and USB 3.0. Repo EmbeddedEra/Switched_USB_Hub, clone ~/Switched_USB_Hub. Style: same as Garage_Door_Adapter (Project_Template, sch_src.py, SOP-021, EmbeddedEra library only).

Open

  • USB2 pair skew tuning pass on both boards after routing (USBHub2: H1 7, H2 6, P1 -8.5, P3 -11.5 mm from TS3USB30 + stacked USB-A pinouts; USBHub3 H2-H4 0.6-1.5, UP ~1.5); check against the USB 2.0 HS budget, then serpentines. Also USBHub3 P1/P2 cap-to-ESD 25 mm at 1 mm pitch is uncoupled.
  • After routing: Update Footprints from Library on both boards for the 3D-model fixes (usb-hub-parts 7b8f95e: HD3SS3220 rot +90, ShouHan USB-C z, Jing USB3-A z, UJ2 offset+colour); then re-render the project page. ShouHan/Jing/HRO overhang UNVERIFIED (no datasheet).
  • Review/merge EmbeddedEra/Project_Template PR #2 (title block 005 + GDA text vars; template still had 003).
  • USBHub3 J201 (USB-C) DRC exemptions added by worker at 43fb5b9: own-pad clearance 0.15 + hole_clearance 0.15 (GDA precedent 0.2) and annular_width min 0 (overlapping GND shield-tab pads). Likely a footprint fix on usb-hub-parts; blocks fab, owner call.
  • ERP IPNs for the 15 new library symbols on branch usb-hub-parts (all blank).
  • Set KICAD_LIB_TOKEN secret on the repo (CI).
  • USB7206C LCSC stock only 20 (Digi-Key 4151): consign or buy before JLC assembly.
  • Unproven: crystal load caps, USB-C/USB-A/150 uF land patterns (no mfr drawing), MCP strap sampling on hub port.
  • Merge library branch usb-hub-parts to master after the boards pass.

Decisions

  • 2026-10-30 owner: parts on one side only (single-sided assembly); 2.0 board 2 layers, 3.0 board 4 layers (JLC stackup).
  • 2026-10-30 owner: two boards, one repo.
  • 2026-10-30 owner: physical data cut on the USB 2.0 lines per port (TS3USB30), SuperSpeed disabled logically by the hub.
  • 2026-10-30 owner: USB-C upstream, 4x USB-A downstream, external 5 V input.
  • 2026-10-30 owner: Windows control through a driverless HID GPIO bridge (MCP2221A) on an internal hub port; Linux/macOS also via uhubctl (hub-class PORT_POWER). Scout: uhubctl README says Windows cannot switch hub ports (winusb.sys).

Handoff (2026-10-30, chat over budget)

  • Repo ~/Switched_USB_Hub (main 5950f7a: plan, design-notes, both schematics merged aeccff6, tools/usbhub.py). Library branch usb-hub-parts in ~/kicad-lib-usbhub (c474be9, kicad-check 0 errors); env: export KICAD_LIB=~/kicad-lib-usbhub KICAD_LIB_REPO=~/kicad-lib-usbhub EMBEDDEDERA_DIR=~/kicad-lib-usbhub EMBEDDEDERA_SYMBOL_DIR=~/kicad-lib-usbhub/symbols EMBEDDEDERA_FOOTPRINT_DIR=~/kicad-lib-usbhub/footprints.
  • Routing workers were running when this chat ended (they commit + push each stage): USBHub2 worker FINISHED (not routed): ~/Switched_USB_Hub-hub2 branch hub2-pcb at a25f508 (5c1a75f re-placement kept, all copper stripped, GND fan-out 84 vias, 9 pads without via: U301.19 + TS3 pins 5/9 on U503/U523/U603/U623; +5V must be re-routed). USB2 class now 0.5 track / 0.2 pair gap / 0.2 pour gap = 97.9-98.4 ohm (documents/zdiff.py), no rule loosened. DRC 4 errors (starved thermal) / 211 unconnected; 321 ratsnest crossings. Blockers: hub upstream pair exits left but J101 is right; PRTPWR/OCS must cross the x140-147 downstream bus (slow nets on B.Cu); each TS3 splits D+/D- ~4.3 mm apart. Its next steps: one script for waypoint -> coupled 45-degree pairs with necks, route 10 pairs on F.Cu, lock, B.Cu keepouts under them, then +5V, then Freerouting; USBHub3 worker STOPPED at turn limit, no report: ~/Switched_USB_Hub-hub3 branch hub3-pcb at 43fb5b9 (pushed; stage 1: USB2/USB3 classes 0.28/0.20 = 90 ohm own FD solve, J201 scoped own-pads rule, AC caps moved into lanes, U202/U203 lane sets swapped for uncrossed mux fan-out; ERC 0/0, DRC 0 errors / 414 unconnected, no routing). Uncommitted, unreviewed: hardware/USBHub3/pair_hops.py and route_pairs.py (its pair-routing script in progress; read before reuse). Each board's plan: hardware//documents/ROUTING-PLAN.md.
  • Next action: git -C ~/Switched_USB_Hub-hubN log --oneline -5 + git status; if a branch is not at DRC 0 errors / 0 unconnected, continue routing from its ROUTING-PLAN (fresh worker per board, commit per stage). Then verify each board yourself (kicad-cli pcb drc --schematic-parity, sch erc, render, STEP 0 missing), merge hub2-pcb/hub3-pcb to main, republish project page (see Log), merge usb-hub-parts to library master after kicad-check.
  • Not proven: USBHub3 HD3SS3220 SS lane orientation, USB7206C RESET_N circuit, CFG_STRAP "Configuration 3", crystal load caps both boards, USB-C/USB-A/150 uF land patterns, buck divider vs TLV62569 range; no reverse-polarity on the 5 V terminal. JLC impedance calculator not run for USBHub3 pairs.

Log

  • 2026-10-30: USBHub2 on 4 layers (9d2213e): 8/10 pairs routed, DRC 0 errors, 203 unconnected (d0af686). USBHub3 b02afac: SS lanes, USB_UP, In2 pours, Freerouting 40 nets, DRC 0 errors, 234 unconnected.
  • 2026-10-30: schematics redrawn GDA style (template 005, A4, wired paths): USBHub2 bbbf573, USBHub3 1110374; ERC 0, overlap 0 all sheets, netlists identical except strap renames (verified).
  • 2026-10-30: owner: more layers or a bigger board are fine (supersedes 'USBHub2 stays 2 layers'). Decision: USBHub2 -> 4 layers JLC04161H-7628, USB2 pairs 0.28/0.20 = 90 ohm like USBHub3; USBHub3 may grow in 5 mm steps. State: hub2-pcb 243963f (H1,H3,H5 routed at 0.5/0.2, to re-route), hub3-pcb d8b89ad (H1-H4 routed, DRC 0 errors, 345 unconnected).
  • 2026-10-30: owner: U201 model wrong + USB models need work -> fixed in library 7b8f95e (renders checked: scratchpad/after/*). USBHub2 neck rules work: H5+H1 routed (fc5932d), H1 skew 6.36 mm to tune later.
  • 2026-10-30: USBHub3 eeroute on every pair: 0 pairs complete (fa28589 = VCORE vias only). Blocker on both boards: pair cannot launch from fine-pitch pads (U301 0.4 mm pitch vs 0.48 pair pitch; also AC caps/ESD ends) - eeroute pair walker has no neck-down. Testing courtyard neck rules on USBHub2 first, then same on USBHub3. Partial outputs: scratchpad/h3/o_*.
  • 2026-10-30: project page (Artifact) https://claude.ai/artifact/1KwLNYFwzWcKsKMMRFrz8K built by tools/project_page/build.py <out> (main 0deaf31, PCB_ env points at routing worktrees); republish after each design change; status.json holds stage/decisions/open.
  • 2026-10-30: pair routing switched to existing ~/eeroute (KiCad PNS diff-pair router) instead of new scripts (hard rule 1); hub3 worker 2 ended with no copper at cec307c.
  • 2026-10-30: owner: no handoff, continue routing in the same chat (overrides the budget handoff); both routing workers resumed.
  • 2026-10-30: USBHub2 pairs 0.5/0.2 (pour gap 0.2) = ~98 ohm, under the 2-layer 100 ohm target; hub2-pcb a25f508 placed, unrouted.
  • 2026-10-30 owner: USBHub2 stays 2 layers ("2 is fine"); USB pairs target <=100 ohm coplanar, measured value goes in its ROUTING-PLAN.
  • 2026-10-30: schematics merged to main aeccff6 (USBHub2 7 sheets/118 parts, USBHub3 7 sheets/131 parts, ERC 0/0, overlap 0, tidy pass). Library fixes 46831cc (MCP2221A GP2 pin y), TPS2065/USB2517 pins power_in. tools/usbhub.py 5950f7a (MCP via EasyMCP2221 / uhubctl), logic tested with a fake device only. PCB workers on branches hub2-pcb (80x50, 2L, placement 68b20a0; owner-precedent J101 scoped rule from GDA_Main approved) and hub3-pcb (4L JLC04161H-7628).
  • 2026-10-30: repo created (private, Project_Template), plan 20221f2; chips USB2517 (hub2) + USB7206C (hub3, 5 SS + 1 USB2 port) + MCP2221A; VL817 rejected (no stock). Board folders a2d473f. Library usb-hub-parts c6cb464 (15 parts, models, kicad-check 0 errors); design-notes 8ab43cf. Schematics in worktrees ~/Switched_USB_Hub-hub2 / -hub3 (branches hub2-sch / hub3-sch).
  • 2026-10-30: started. Scout: USB2514B (C58940) per-port power, uhubctl lists 0424:2514 hubs; VL817 (C209756) strongest uhubctl evidence for 3.0; USB5744 out of stock on LCSC.
  • 2026-10-30: step 1 done. Datasheet items proven in Switched_USB_Hub/docs/design-notes.md; 15 symbols + 8 footprints/models on KiCad branch usb-hub-parts (not merged, IPNs blank, no erp-sync pull). Polarity: AND(PRTPWR/PRT_CTL, MCP GPn), high=ON, 100k pull-ups, flash GP=1 in production. Unproven: see design-notes section 6.
  • 2026-10-30 eeroute C++ global router built (fork target eeroute_global, ~/kicad-fork ff to github/eeroute 456a2de, ~/eeroute ff to origin/main 0a1752b). USBHub3, 52 unrouted signal nets on F/B: native 2.8 s vs Python 98 s, same overflow (28 vs 27) — the remaining nets do not fit on 2 signal layers as placed; hot spots J421 and the C441-C444/R441 cluster (port 2/3). Upstream bug: eeroute_route.py now imports global_route (numpy/pillow/scipy) but declared no deps, so uv run failed (chain pairs SS_P4_RX/TX, SS_UP_RX); fixed locally in ~/eeroute, uncommitted. All 7 earlier SS pairs in the chain timed out at 720 s with the old code.
  • 2026-10-30 CORRECTION to the earlier eeroute line: hot spots were read with x/y swapped (global_route writes overflow_tiles as [layer, y, x, over]). Real crowding is at the U301 pin escapes and around U201/ESDs, plus J421 for USB_P1. In2 offered as a signal layer was used (379 tiles) and did not change overflow; finer tiles 0.6/0.4 mm give 25.0; --fine leaves 7 boxed-in pads unroutable: USB_P1_D+/D- at J421 (113.85,151 / 117.25,156.95), SS_C_RX1_N at U201 (166.4,120.25) and J201 B-row (173.71,119.88), SS_P2_RX_P/N (132.55/133.05,160.58), SS_P4_TX_N at U301 (143.6,133.85). Next: free those pads (stage per pad). TX1 at J201 needs a P/N crossover; USB 3 receiver polarity inversion to be confirmed from the spec before swapping in sch_src.py. eeroute dep fix committed locally on main (branch fix/route-deps), not pushed.
  • 2026-10-30 Routing state (local commits, none pushed after the CI rule). USBHub2 hub2-pcb ad5f70f: DRC 0 err / 26 unconnected; X301 crystal boxed in by locked USB_H1/H2 diagonals → worker ripping H1/H2, moving X301, rerouting. USBHub3 hub3-pcb 4e2d8d7: DRC 0 / 185, U301 SS fan-out stubs (ss_lanes.py --fanout); eeroute cannot route coupled SS pairs from U301 (9 of 9 fail; SS_P3_RX only uncoupled, skew 1.65 mm). Decision: floorplan v2 on branch hub3-floorplan2 (worktree ~/Switched_USB_Hub-hub3fp) — place caps/ESD/connectors in line with U301 SS pin groups and lay straight lanes with ss_lanes.py; bigger board allowed. Open: USB_UP on In2 at 0.28 (not 90 Ω), TX1 P/N crossover (confirm USB3 polarity inversion), J201 exemptions.
  • 2026-10-30: USBHub3 floorplan v2 (branch hub3-floorplan2, local, 31806c2): board 120x80, 16/16 downstream SS pairs laid straight on F.Cu by ss_lanes.py, no vias, skew <=1.24 mm (P1 TX worst). DRC verified by me: 0 errors, 244 unconnected. Next: UP lane (J201 rotate, ESD, U201, caps to U301), then shorten the 0.2 mm neck legs (up to 12 mm on RX4), then support-circuit placement.
  • 2026-10-30: USBHub2 e9e3bf9 (local): X301 moved 1.5 mm west, XTAL1/RBIAS/VDD18PLL routed, H1/H2 ripped. Verified 0 errors / 27 unconnected. eeroute H1 needs >600 s (PNS 420 s x3); rerunning with 1800 s. Crystal load caps still far (loop not short) — fix before fab.
  • 2026-10-30: USBHub3 6e8a751 (local): upstream SS stack placed (J201 north, mux U201 feeding U301), UP RX/TX + RX2 + TX1 lanes laid. Verified 0 errors / 342 unconnected (J201/U201 support nets ripped). Decision: SS P/N swaps (UP RX, UP TX, TX1, maybe RX1) resolved by polarity inversion in sch_src.py, not via swaps; USB 3.x 6.4.2 receivers correct lane polarity (TI E2E confirms). SS only, never USB 2.0. Worker doing the swap + merge of hub3-sch2.
  • 2026-10-30: USBHub3 d5e0c70 (local): hub3-sch2 merged into hub3-floorplan2; SS P/N swaps done in sch_src.py (UP RX at U201, UP TX at C201/C202, TX1 J201 A2/A3, RX1 J201 B10/B11); gaps closed straight, no vias. Verified: DRC 0 errors / 336 unconnected, parity 582/582 0 mismatches (new tools/parity.py), ERC 0 errors. Next: TX2/RX1 B-row + U202/U203 flow-through bridges.
  • 2026-10-30: USBHub3 2b9bf0b (local): all 8 upstream-side SS_C lanes routed (TX2/RX1 via B.Cu, 2 vias/net, skew <=0.05 mm), ESD flow-through bridges. Verified 0 errors / 322 unconnected. Found regression: 6e8a751 floorplan3.py rip deleted downstream SS_P1..P4 lane copper from 31806c2 (worker report missed it); restore worker running.
  • 2026-10-30: USBHub3 d946d91 (local): downstream SS lanes restored (floorplan3.py rip regex fixed). Verified 0 errors / 266 unconnected, no SS_* open, parity 0. Found: B.Cu/In1/In2 zones still start at y=99.95 after board grew north to y=77.
  • 2026-10-30 HANDOFF (chat long): state = USBHub2 hub2-pcb e9e3bf9 (0 err / 27 unc; H1/H2 ripped; worker laying H1/H2 as scripted coupled pairs + moving X301 load caps). USBHub3 hub3-floorplan2 d946d91 (0 err / 266 unc; worker extending planes to new outline + stitching vias, then function-grouped support placement). All local, nothing pushed since CI rule. Every hub3 brief must include the PROTECTED COPPER check (net_len.py 'SS_|USB_' diff, no net may shrink). Fab blockers still open: 0.2 mm neck legs up to ~12 mm (script check: 0.2 mm length per SS net <= ~2 mm), P1 TX skew 1.24 mm, USB_UP to re-lay as F.Cu coupled 90-ohm pair via ss_poly.py, run_all.sh never run end to end, stale zone fills in commits, J201 DRC exemptions. eeroute rejected for H1 (single-ended fallback, 2.76 mm skew). Next action: verify each worker commit (DRC on temp copy + parity + protected-copper diff), then Freerouting in small groups.
  • 2026-10-30: USBHub3 0da7017 (local): planes extended to y=77, 66 stitching vias (tools/stitch.py). Verified 0 errors / 196 unconnected, SS_/USB_ copper unchanged. 36 GND/+3.3V pads in dense spots need hand vias. Next running: function-grouped support placement.
  • 2026-10-30: USBHub2 34c43e4 (local): crystal caps moved close (C302 2.15 mm stub; C301 5.8 mm, limited by courtyard). H1/H2 still open: no clear new single-layer corridor. Decision: restore the original H1/H2 pair copper from ad5f70f and re-route the short nets (VDD18PLL, RBIAS, XTAL1, X301 GND via) around it (26 conflicts, mostly VDD18PLL vs H2_D+). Worker running.
  • 2026-10-30: USBHub3 c8f9bb0 + stitch.py fix (local): function-grouped placement (tools/floorplan4.py). Verified 0 errors / 199 unconnected, ratsnest 3178->1984 mm, parity 0, SS_/USB_ copper unchanged. Not ideal yet: P1/P2 switches+ESDs still at y148-160 (carry USB_P* copper), U481/U482 ~20 mm from J481, VBUS_DET divider near D101, J101 orientation UNVERIFIED.
  • 2026-10-30: USBHub2: restore-old-H1/H2 path REJECTED (old pairs 8.17/6.16 mm skew, uncoupled; fitting them needed XTAL1 on an In2 jumper + via-in-pad on crystal; RBIAS/VDD18PLL still boxed). Correction: old skews are not fixable by tuning, pairs need a redo. Decision: re-place the U301 pin 1-4 / pin 60-63 corner (U503/U523 facing pins 1-4, corridor cleared, crystal group short on F.Cu), then lay H1/H2 coupled with ss_poly.py. USB2 intra-pair skew limit used: <=1.25 mm (50 mil). 34c43e4 trailer amended; verified 0 err / 27 unc.
  • 2026-10-30: USBHub2: every USB2 pair fails skew (P1 8.5, P3 11.5, H4 5.0, UP 3.7 mm; H1/H2 unroutable). Cause: TS3USB30 switches 22-27 mm west of U301, D+/D- on opposite package sides; U301 pins 1-4 and crystal pins 60-63 exit the same SW corner. Decision: USBHub2 floorplan v2 on new local branch hub2-floorplan2 (worktree ~/Switched_USB_Hub-hub2fp, from 7f50f1d), same method as USBHub3; hub2-pcb kept as fallback.
  • 2026-10-30: USBHub3 891d932 (local): J101 rot 270, entry faces west edge (evidence: 3D render only); VCORE/+5V autorouted with SS/USB locked. Verified 0 err / 175 unc, SS_/USB_ copper unchanged. Board J101 copy has no 3D model line though the library footprint has one -> covered by the pending footprint update. Next running: USB_UP coupled F.Cu re-lay, VBUS, control nets, downstream USB2 pairs.
  • 2026-10-30: USBHub2 floorplan v2 3e17b01 (local, hub2-floorplan2): board 80x80, every USB2 pair laid coupled (H1-H5, P1-P4, UP), skew <=0.30 mm (was up to 11.5). Verified 0 err / 181 unc, parity 411/411, no USB_* pair open. Open: crystal/RBIAS/VDD18PLL routing, 39 parked parts in north strip, P2/P4 D- on B.Cu (2 vias), UP on B.Cu (4 vias), skew bumps in uncoupled stretches. Worker running crystal + placement + stitch.
  • 2026-10-30: USBHub2 601ee0a (local): crystal group re-routed on F.Cu, no vias (C312 2 mm from pin 62; C301/R301 3-4 mm). Verified 0 err / 172 unc, USB copper unchanged. Next running: parked-strip placement + stitching.
  • 2026-10-30: USBHub3 da11ec0 (local): VBUS (0.6 mm), VCORE regulator nets, PRT_CTL/EN/RESET/straps routed. Verified 0 err / 134 unc, SS_/USB_ copper unchanged. Fix kept: netclass pattern VBUS_P? -> *VBUS_P? (sheet-prefixed names missed it). USB_UP still blocked at U301 (SS_UP_TX stubs + VCORE B.Cu diagonal); worker running USB2 pairs with permission to reroute that VCORE.
  • 2026-10-30: USBHub2 6a7884a (local): 39 parked parts placed by function (ratsnest 1905->811 mm incl. stitching), 61 stitch vias. Verified 0 err / 109 unc, USB+crystal copper unchanged. Check U501/U601 placement (pulled toward MCP_GP). Next running: hand stitches for 16 pads, autoroute groups, maybe shrink empty north strip.
  • 2026-10-30: USBHub3 USB2 pairs (UP, P1-P4) FAILED to route at da11ec0: floorplan v2 laid SS lanes without planning USB2; J201 A/B rows walled by SS copper, U301 USB2 pads boxed by SS stubs/lanes. Decisions pending/next: (1) explicit breakout rule for scripted pairs (max uncoupled length per end from TI SPRAAR7, skew <=1.25 mm) — whole-pair single-ended stays FAIL; (2) named exception to protected copper: SS_C lanes near J201 and SS_UP_TX stubs may be re-laid by ss_poly.py if skew no worse, no new SS vias, others unchanged; (3) map each USB2 chain first; (4) J201 A/B D+/D- join = one crossing, counts against breakout; (5) no USB2 on B.Cu across In2 splits.
  • 2026-10-30: DECISION (USB2 pair rule, both boards, source TI SPRAAR7J App. A + Sec 2.4/3.3/3.6/3.9): intra-pair skew <=50 mil (1.27 mm); uncoupled breakout only within 0.25 in (6.35 mm) of a package/connector, as short as possible; <=4 vias per trace, equal via count on D+ and D-; never cross a reference-plane split (else 1 uF-or-less stitching cap + vias within 200 mil). Whole-pair single-ended (eeroute fallback) stays FAIL. Microchip AN26.2 not yet checked.
  • 2026-10-30: USBHub3 db338db (local): ROUTING-PLAN.md chain map for 5 USB2 chains (UP, H1-H4 hub side, P1-P4 port side); still 0 USB2 pairs routed. Decision: USB_* copper on hub3 is leftover, not protected (protect SS_ only); rip all USB2 copper, treat TS3USB30/USB2 ESD/U204 as movable, prove one chain (P3) go/no-go before scaling; for UP move U204 west of SS_C_RX2 before touching SS. If P3 fails with parts free to move -> ask Angel about 6 layers (would force SS width recalculation and re-lay).
  • 2026-10-30: USBHub3 54addd9 (local): all USB2 copper ripped (none was complete). Verified 0 err / 125 unc, SS_ unchanged. P3 proof: hub segment H3 routes coupled on F.Cu (skew 0.06); J461 D+/D- sit behind the SS row -> method: split around GND pad 7 within the 6.35 mm breakout allowance, one equal-via swap on H3 for polarity. Worker proving H3+P3.
  • 2026-10-30: USBHub2 8fc55d1 (local): VBUS/+5V/BUCK/VDD18 + PRTPWR/OCS/PORT1-2_EN autorouted. Verified 0 err / 69 unc, USB+crystal segment lengths unchanged. New open item USB_UP_D- (via 169.04,120.74 to F.Cu track) appeared in 8fc55d1 with identical USB copper and footprints, cause unknown; worker investigating + finishing routing.
  • 2026-10-30: USBHub3 P3 pilot NO-GO again: real blocker is Freerouting power copper (VBUS_P2/P3 0.6 mm on F.Cu through U463, +5V on B.Cu) routed before USB2. LESSON (both boards): route USB pairs before autorouting power/control (USBHub2 did and succeeded). Decision: rip autorouted non-SS copper from 891d932..da11ec0, route USB2 pairs first with mux/ESD free to move/rotate, re-autoroute power/control after.
  • 2026-10-30: USBHub2 23fdf2b (local): stray via (was CC2, net tag flipped to USB_UP_D-) removed; one more autoroute group. Verified 0 err / 67 unc, protected copper same. Correction: I had checked 6a7884a, not ebcf8e9, when I said the UP open was new in 8fc55d1. Grouped autoroute gains ~1 net per run; next: one global Freerouting pass over all non-protected nets (rip earlier autoroute copper on a scratch copy, adopt only if better).
  • 2026-10-30: USBHub3 782745f (local): autorouted power/control copper ripped (ef96db5, 593 items); U463 rotated 180, H3 routed coupled F.Cu 0 vias skew 0.50 mm — first USB2 pair on USBHub3. Verified 0 err / 193 unc, SS_ unchanged. Issue: H3 at 0.2 mm width full length (USB2 class 0.28) -> widen outside U301 neck. Next running: P3 (rotate ESD U464), then H4/P4.
  • 2026-10-30: USBHub3 c070af9 (local): H3 widened to 0.28/0.2 (0.2 only in 1.9 mm U301 neck), skew 0.47, 0 vias. P3: one P/N crossing is topologically required (U301 D+ west vs J461 needs D- west from north) -> decision: B.Cu via hop, equal 2 vias per member, over full-board In2 region (x>=129). Worker running P3 then H4/P4.
  • 2026-10-30: USBHub2 85b15b6 (local): global Freerouting pass (rip earlier autoroute copper, one run over 40 nets, --passes 100) + stitch2: 67 -> 49 unconnected. Verified 0 err / 49, protected copper+vias same. LESSON: one global autoroute beats small groups. Next: hand-route short ones, check In2 signal tracks splitting +3.3V plane, second global pass.
  • 2026-10-30: USBHub3 0bb402e (local): P3 routed (2 vias/member, skew 0.12). Verified 0 err / 189 unc, SS_ + H3 unchanged. Caveat: only ~7 of 25.7 mm coupled; mux-to-ESD leg ~10 mm uncoupled (pins 4.3 mm apart with H3 between) — every point within 6.35 mm of U463/U464 so it meets the letter of the TI rule, not the spirit; review before fab. Next running: H4/P4, then H1/P1, H2/P2.
  • 2026-10-30: USBHub2 46e28c0 (local): HUB_RESET_N moved off In2 (In2 now plane only), board shrunk back to 80x50 (100,100)-(180,150). Verified 0 err / 43 unc, protected same. Freerouting stalls on ~20 signal nets + 23 GND/3V3/5V pads; next: C++ global-router feasibility map + hand fixes; if U301 area over capacity -> decide bigger board vs 6 layers.
  • 2026-10-30 HANDOFF (supersedes the earlier one): all local, nothing pushed since the CI rule.
  • USBHub2: branch hub2-floorplan2, worktree ~/Switched_USB_Hub-hub2fp, HEAD 46e28c0: 80x50 board, all USB2 pairs + crystal laid, 0 err / 43 unc. Running: USB2 pair audit vs the TI rule (P2/P4 unequal vias, UP In2 region unknown) + fix, and a global-router test around U301 (ordering vs capacity). If ORDERING: scripted U301 fan-out then one global autoroute; if CAPACITY: decide bigger board vs 6 layers. hub2-pcb (7f50f1d) = old fallback.
  • USBHub3: branch hub3-floorplan2, worktree ~/Switched_USB_Hub-hub3fp, HEAD 03f45cf: all SS lanes, H3/P3/H4 USB2 pairs, 0 err / 187 unc (power/control deliberately ripped, re-route AFTER all USB2 pairs). Running: TS3USB30 90-degree rotation trial for H4 (current 10.3 mm uncoupled), then P4; then H1/P1, H2/P2, UP (move U204 west of SS_C_RX2). Then one global autoroute of power/control.
  • Rules in force: USB2 TI SPRAAR7J rule (logged above); protected-copper diff every commit; check scripts moving from /tmp into each repo's tools/.
  • Fab blockers: SS 0.2 mm neck legs up to 12 mm, P1 TX skew 1.24 mm, P3 ~10 mm uncoupled mux-to-ESD, J201 DRC exemptions, footprint/3D model update (J101 model missing on hub3), Microchip AN26.2 not checked, run_all.sh never run end to end, stale zone fills.
  • 2026-10-30: USBHub2 c9bd9cc (local): USB2 audit (tools/usb2_audit.py, ROUTING-PLAN.md); UP and H2-H4 fixed to pass; H5, P2, P4 still fail (unequal vias / uncoupled). U301 test: unroutable 0 but overflow 5 at F.Cu pin ring, router does not converge -> marginal capacity. DECISION: no 6 layers yet; allow short (<=5 mm) signal escapes on In2 near U301 (not under B.Cu USB pairs, +3.3V fill must stay one piece), scripted fan-out then one global autoroute.
  • 2026-10-30: USBHub2 cd23ccd: H5 fixed (2/2 vias, skew 0.24). Verified 0 err / 43 unc, parity 0; audit: all pass except P2/P4 (worker running). Review item: hub2 P1/P3 run 1.9 mm apart (uncoupled) for 16 mm, passing only because every point is within 6.35 mm of a part; also 192 track_angle warnings to clean. USBHub3 16ea762: P4 routed (skew 0.007, 2/2 vias), verified 0 err / 183 unc, SS_+USB protected same. TS3USB30 puts D+/D- on opposite columns at any rotation -> 5-10 mm split near it is a device constraint (rotation trial rejected: shorts, no gain). Next: hub3 H1/P1, H2/P2.
  • 2026-10-31: USBHub2 57cae46 (local): P2/P4 coupled on B.Cu, 1 via each -> ALL USB2 pairs pass the TI audit (tools/usb2_audit.py). Verified 0 err / 43 unc, parity 0. Worker running U301 fan-out with short In2 escapes. USBHub3 fb31c7c (local): H1 (skew 0.001, 2/2 vias) and P1 (skew 0.000, 1/1) routed; verified 0 err / 180 unc, SS_+USB protected same. H1 D- B.Cu 0.36 mm from VCORE island corner (below 1.5W) — nudge requested. Next: hub3 H2/P2, then UP.
  • 2026-10-31: USBHub3 b9feede (local): H2 (skew 0.000) and P2 (skew 0.002, 1/1 via swap) routed; H1 nudged to 0.46 mm from VCORE island. Verified 0 err / 176 unc, SS_+USB protected same. P2 B.Cu crosses the In2 +5V strip edge (H3 F.Cu sits on the edge) -> fix: reshape +5V zone locally, else TI stitching cap (<=1 uF) at the crossing. USBHub2 bb74a53: PRT_DIS + strap routed, 41 unc, audit 0 FAIL, In2 one polygon; worker ripping U301 ring and re-routing.
  • 2026-10-31: USBHub2 60f9a23 (reroute_ring.py) verified: 0 errors, 38 unconnected, parity 0, audit 0 FAIL, prot same, +3.3V In2 1 polygon. Next worker routes the rest. Local only.
  • 2026-10-31: DECISION USBHub3 upstream ESD: U204 USBLC6-2SC6 (SOT-23-6) does not fit the J201 corridor; the only 4-via layout put it 28 mm from J201. Swap to a smaller flow-through part (TPD4E05U06 first, already on BOM) placed at the connector; UP then 3 vias per member. Worker running; local only.
  • 2026-10-31: USBHub3 78ee40f verified (U204 -> TPD4E05U06 at J201, 2.2 mm; ERC 0, DRC 0 errors, 177 unconnected, parity 0, SS/USB protected unchanged). Deviation: VBUS_UP lost the USBLC6 rail clamp (no ESD on VBUS_UP at J201); pcb_src.py still has the old U204 line. UP routing worker running (4/4 vias target).
  • 2026-10-31: USBHub2 78ee532 verified (route_rest.py global reroute): 0 errors, 36 unconnected (23 power/GND, 3 VBUS_UP, 10 signal), parity 0, audit 0 FAIL, prot same, In2 1 polygon. Global autoroute is slow (~20 min, +2); next worker fixes per net (route_last.py).
  • 2026-10-31: USBHub3 f79e7e2 verified: USB_UP routed 44.095/44.100 mm, 4 vias/member, longest uncoupled 4.89 mm (J201 hop), scoped .dru 0.15 mm J201 join rule. All USB2+SS pairs done; DRC 0 errors, 169 unconnected, parity 0. Next: power/control (route_power.py) worker running.
  • 2026-10-31: DECISION (supersedes "In2 escapes ≤5 mm"): USBHub2 control nets may run on In2 at any length, gated by: +3.3V In2 fill 1 polygon with all +3.3V pads connected; no In2 slot within 0.55 mm of a B.Cu USB pair centreline (audit edge check added); +5V island not split. 6 layers only as last resort (stackup change would invalidate 90-ohm 0.28/0.2 pairs). USBHub2 03986de verified: 35 unconnected, 0 errors.
  • 2026-10-31: USBHub3 USB_UP independently re-checked: coupling 2.23/4.89 mm longest uncoupled, skew 0.004, 4/4 vias, In2 +3.3V edge 5.9/6.2 mm OK.
  • 2026-10-31: USBHub2 c462730 (stitch2 fix, 12 vias, 35->28 unconnected) + c363b70 (usb2_audit In2 edge/void check >=0.55 mm). New check shows pre-existing FAILs: P2 0.07, P4 0.24, UP 0.15/0.21 mm (likely other-net via antipads under the pairs); fix_in2_edges worker running. 9 signal nets still open (In2 autoroute too slow, untested).
  • 2026-10-31: DECISION USBHub2 In2 edge check: voids from pads of the pair's own connector within 6.35 mm are exempt (breakout region, same basis as the coupling exemption), reported as EXEMPT and listed in ROUTING-PLAN deviations. Causes: P2/P4 = J501/J601 shield THT voids; UP = C503.2 GND via and MCP_RST_N via antipads (to be moved). 39cb130 adds tools/fix_in2_edges.py only.
  • 2026-10-31: USBHub3 2ccba98/9262655/40a1ffc verified: 169->98 unconnected, 0 errors, parity 0, SS/USB unchanged. Found: J201 CC1/VBUS_UP escapes blocked by the USB_UP D+ bridge vias (UP worker's escape estimate was wrong); stray USB_P1 F.Cu stubs since <=f79e7e2; solid zone-connect on J481.7/J201 shield pads done by sed, not scripted. Worker on J201 re-plan + stubs + +5V/VCORE stitching.
  • 2026-10-31: USBHub2 d8222c2 verified: audit 0 FAIL (UP voids fixed by moving 6 other-net vias, fix_up_voids.py), 0 errors, 28 unconnected, prot same, In2 1 polygon. Next: route_in2.py for 9 control nets.
  • 2026-10-31: USBHub3 at 93 unconnected. Found USB_H6_D± (hub port 6 -> MCP2221A U501) was never routed; 8 opens are flow-through ESD internal joins (U424/444/464/484 pins 1-6, 3-4), not stubs (correction of an earlier claim). Worker on H6 + under-body bridges; read-only plan for J201 corner (may move SS corner copper) and VCORE/+5V distribution (pads outside In2 regions).
  • 2026-10-31: USBHub3 8b665b2 H6 routed (54.128 mm, skew 0, 4/4 vias, In2 OK; deviation: 0.2 neck 2.9 mm past U301 courtyard, FS-only pair) + 12fb4da ESD bridges 5/8; verified 0 errors, 86 unconnected, parity 0, SS unchanged. Next worker: jumper_pad_groups for USBLC6 internal joins (replaces bridges; library follow-up), then J201 corner per scratchpad/hub3_plan_keep/hub3_plan.md (intentional SS RX2 shift).
  • 2026-10-31: USBHub2 20f21f2 verified: 5 control nets on In2 (route_in2.py), 23 unconnected, 0 errors, audit 0 FAIL, prot same, In2 +3.3V 1 polygon. Open: PRTPWR1/3, OCS3_N (via sites), PRTPWR4 (splits plane), stitch2 crash.
  • 2026-10-31: USBHub3 e931bf4 (USBLC6 jumper_pad_groups 1-6/3-4 replaces bridges; library follow-up in ROUTING-PLAN) + 41bb59d (J201 corner; SS_C_RX2 intentionally 23.98->24.43 mm, skew 0.004; UP 43.196/43.877 skew 0.68, 4/4 vias, longest uncoupled 6.28 next to U204) verified: 0 errors, 80 unconnected, parity 0. Open: VBUS_UP pads, CC1 route, In2 void check port to USBHub3, VCORE/+5V distribution.
  • 2026-10-31: USBHub3 a18413c: in2_voids.py (void check port) + fix_in2_voids.py moved 15 vias; 8 FAILs remain. Checker gaps: skipped UP/H3/SS pairs; in2_check.py vs in2_voids disagree (H1 0.46 vs 0.15) — earlier USBHub3 In2 PASSes (H1/H2/H6/P1/P2/UP) unverified until fixed. J201 VBUS/CC1 pocket is closed on F.Cu and B.Cu by SS pairs on both sides; only In2 or a stackup change opens it. Scout checking JLC 6-layer outer-layer impedance match. USBHub2 b27ac38: stitch2 sort fix; U301 east pin via assignment worker running.
  • 2026-10-31: DECISION USBHub3 -> 6 layers, JLC06161H-7628 (L1-L2 7628 0.2104 mm = same as current JLC04161H-7628, so routed outer pairs keep 0.28/0.2 geometry; scout via jlcpcb.com/impedance, Ω to confirm with kicad-stackup/JLC calculator). Reason: B.Cu pairs referencing the split In2 cause the In2 edge FAILs, the closed J201 VBUS/CC1 pocket and the VCORE/+5V reach problem; 6L gives B.Cu a solid GND reference (L5) and inner layers for power/VBUS/CC1. Owner allowed more layers 2026-10-30. Cost: 6L ~1.5-2x 4L at proto qty (unverified, quote needed). USBHub2 stays 4L.
  • 2026-10-31: USBHub3 2ae2186 verified: 6 layers JLC06161H-7628 (L1-L2 and L5-L6 7628 0.2104 mm Er 4.4 = old L1-L2, so pair geometry unchanged), In3 empty power/signal, In4 solid GND; 0 errors, 80 unconnected, parity 0, SS/USB unchanged. in2_voids now vs In4: 9 FAILs (3 other-net via antipads, rest near USB-A connectors, cause TBD). in2_check.py removed (measured outlines, not fill). Worker: voids, VBUS_UP/CC1 on In3, VCORE/+5V on In3.
  • 2026-10-31: USBHub3 6fe0634 verified by worker gate: In4 GND solid pad connect (thermal voids were the P1/P2/P4 FAILs), in2_voids parser fix (newline-eating regex skipped adjacent vias/segments), redundant EN_VCORE via removed; 4 FAILs left (H1_D+ by H2 via, H2_D+/H1_D- by CFG_STRAP vias, TX2_N 0.549). Checked: USBHub2 usb2_audit parses all 1602 segments (no such bug). Worker on VBUS_UP/CC1 via In3 + exemption tightening.
  • 2026-10-31: DECISION USBHub2 In2 gate: '+3.3V fill = 1 polygon' was a proxy; replaced by: usb2_audit 0 FAIL (B.Cu pairs vs In2 edges/voids), all +3.3V pads connected (<=7 baseline opens), every +3.3V In2 polygon stitched by >=2 +3.3V vias/pads, +5V island unsplit. Slow control nets may detour on In2. Reason: U301 east pocket has no short In2 exit (6cbd075 u301_east.py). USBHub2 stays 4 layers.
  • 2026-10-31: USBHub3 ac4a1f2/4b217a4/e2872ae verified: CC1 routed on In3, exemption tightened, CFG_STRAP1 on In3; 0 errors, 79 unconnected, parity 0, SS/USB unchanged, 4 In4 FAILs (P3_D- GND via, TX2_N 0.549 U204 NC pad void, H1_D+ by H2 via, H2_D+ by STRAP2 via). BLOCKER: J201 VBUS_UP pads unroutable (one legal pocket via site, used by CC1). Scouting JLC 6L via-in-pad (POFV) for VBUS pads.
  • 2026-10-31: USBHub2 fc78bcb verified with gate.sh: OCS3_N/PRTPWR3 on In2, 21 unconnected, 0 errors, audit 0, prot 0, +3.3V In2 3 polygons all stitched (relaxed rule: >10 mm2 needs >=2 vias, sliver 2.3 mm2 via+B.Cu jumper). Open: PRTPWR1 (one via site shared with OCS1_N), PRTPWR4, power stitches. Next: smaller scoped vias for these nets.
  • 2026-10-31: USBHub3 1300cdf verified: VBUS_UP routed at J201 (A4-B9/A9-B4 F.Cu joins, 0.3/0.15 small vias scoped .dru citing JLC 6L 0.15/0.25, In3 0.6 mm to C206/R203), CC1 re-laid; 0 errors, 74 unconnected, parity 0, SS/USB unchanged. DECISION: west VBUS via 0.10 mm from SS_C_TX2_N In4 accepted as connector-breakout deviation (own-connector VBUS net, within 6.35 mm of J201, only site); in2_voids gets a coordinate-keyed ACCEPTED list.
  • 2026-10-31: USBHub3 f8ff84d/1d68009/7488ab5 verified: ACCEPTED list in in2_voids (TX2_N west VBUS via), CFG_STRAP2 on In3 + small via, dangling VBUS_DET stub removed; 0 errors, 74 unconnected; 3 In4 FAILs deferred (H2_D+ 0.40 by STRAP2 via, H1_D+ 0.10 by H2's own via, P3_D- 0.50 by GND via). USBHub2: small 0.45/0.25 vias didn't help (no sites); neighbour-move worker running. USBHub3 power-on-In3 worker running.
  • 2026-10-31: USBHub3 8dcb862/f65df68 verified: In3 VCORE zones (13 vias) + In3 +5V zones (6 vias), 74->56 unconnected, 0 errors, FAILS 3. Found XTAL_O open (track end (139.0,123.0) to Y301.3) and VBUS_DET_HD open since <=1300cdf; worker restoring them, then POFV via-in-pad stitching (free on JLC 6L).
  • 2026-11-02: Branch cleanup (owner: 'do everything recommended'). hub2-sch2 merged into hub2-floorplan2 a523682 (15 /Hub/STRAP_* nets renamed on PCB, no copper moved; verified DRC 0 err / 20 unc, parity 0, audit 0 FAIL, prot 0, In2 PASS, ERC 0 with .kicad_pro + lib env). hub2-floorplan2 + hub3-floorplan2 (c854b5f) pushed as backup. Deleted local+GitHub: hub2-sch, hub3-sch (in main), hub2-pcb, hub3-pcb, hub2-sch2, hub3-sch2 (all contained in the floorplan2 branches); worktrees -hub2/-hub3/-sch2/-sch3 removed. Remaining worktrees: ~/Switched_USB_Hub-hub2fp, ~/Switched_USB_Hub-hub3fp. Routing workers restarted on both.
  • 2026-11-02: USBHub3 1d8b612 verified (worker): 54->14 unconnected, 0 errors, parity 0, SS/USB unchanged, In4 FAILS 3 (unchanged); VBUS_DET_HD routed (CC1 via 0.35 mm west), XTAL_O OK. Open 14: U301 VCORE/+3.3V pins + U201.8/.24 + U202/U203 GND walled by locked pairs (no via site >=1.15 mm from B.Cu pairs). DECISION owner: shift USB_H2 pair 0.2-0.3 mm east to open U301 west VCORE via site (re-verify H2 skew/coupling/vias, update usb_protected.txt for H2 only); via-in-pad/exemptions/microvias not chosen. Worker running.
  • 2026-11-02: USBHub3 0318a08 H2 pair shifted 0.3 mm east (h2_shift.py; skew 0.000, 2/2 vias, 61.991 mm, usb_protected.txt H2 lines updated) + 82cb735 VCORE U301.9/.18 vias. Verified: 0 errors, 12 unconnected, parity 0, SS same, In4 FAILS 2 (H2_D+ cleared). Open 12: U301.25 (blocked by CFG_STRAP1/2 vias), U301 VCORE .31/.93/.78 + 3V3 .99/.88/.79/.43, U201.24/.8, U202/U203 GND islands (walled by SS_C pairs) - no via site without via-in-pad or new void exemption.
  • 2026-11-02: USBHub2 10182a3 verified: 20->10 unconnected (GND/+3.3V/+5V stitches, 8 local commits), 0 errors, parity 0, audit 0 FAIL, prot 0, In2 PASS. Open: U501.3 GND pocket (walled by protected H1/UP), U301.46 (strap vias), R201.1 (BUCK_SW), R403.1, D201.1 +5V power width, VBUS_UP x3, PRTPWR1 (via site shared with OCS1_N). Worker re-sent for the non-protected re-routes; U501.3/PRTPWR1 likely need owner placement call. USBHub3 worker adding owner-approved In4 void exemptions (<=6.35 mm of U301/U201/U202/U203, ACCEPTED list).
  • 2026-11-02: USBHub3 8add09a (U301.99 via, In4 void 0.04 mm from H2_D+ under exemption) verified 11 unc but judged poor. DECISION owner: revert it; allow filled via-in-pad (JLC POFV, free on 6L) for U301 power pins, U201.8/.24, U202/U203 GND pads, no new ACCEPTED void entries; CFG_STRAP1/2 vias may move to free U301.25. POFV must be recorded in fab notes. Worker running.
  • 2026-11-02: USBHub3 930188e verified: 7 unconnected, 0 errors, parity 0, SS/USB same, In4 FAILS 2, no new ACCEPTED (8add09a reverted 5a4fd6e). POFV 0.3/0.15 on U301.25/.78/.79, U201.24, U202/U203 GND; fab.yml via_in_pad POFV. DECISIONS owner: scoped .dru 0.15 mm via-to-pad inside U301/U201/U202/U203 courtyards ACCEPTED (JLC 6L min 0.1); local re-route of H2 near U301 and USB_UP near U201 APPROVED for U301.31/.99, U201.8 (re-verify skew/vias/coupling/voids). Also nudging RBIAS/PORT1_GATE/PRT_CTL1/3 (non-protected) and fixing the TP104 VCORE island.
  • 2026-11-02: USBHub2 f601910: 3 unconnected (U301.44 VBUS_UP, PRTPWR1, U501.3 GND). DECISION owner: U501.3 - build both trials (small U501 shift vs local H1/UP reshape), keep the smaller change, re-verify any pair touched. USBHub3 e5a2a76: 3 unconnected; .88/.43 via-in-pad after PORT1_GATE/PRT_CTL3 moved to In3. Workers running on .99/.31/U201.8 and hub2's last 3.
  • 2026-11-02: USBHub3 ROUTING COMPLETE 4e26dda (pushed hub3-floorplan2), verified by me: DRC 0 errors / 0 unconnected, ERC 0, parity 586/586, SS lanes unchanged, warnings no worse than c854b5f (isolated_copper 1->0), In4 FAILS 2 (pre-existing deferred: P3_D- 0.50 GND via, H1_D+ 0.10 by H2 via). Protected changes (approved): H2 shifted 0.3 mm (61.991, skew 0), USB_UP jogged 1.3 mm east near U201 (44.273/44.954, skew 0.681, 4/4 vias). PORT1_GATE/PRT_CTL3 partly on In3; POFV via-in-pad list in ROUTING-PLAN + fab.yml. Not reviewed: In3 zone fills beyond DRC, FB_3V3 after 0.15 mm jog.
  • 2026-11-02: USBHub2 dec8cdb verified: 1 unconnected (U501.3 GND), 0 errors, parity 0, audit 0, prot 0, In2 PASS. 9732d5f VBUS_UP U301.44, dec8cdb PRTPWR1 (separate via sites, PRTPWR2/OCS3_N/OCS1_N re-routed). U501.3: via site under locked B.Cu USB_UP; plan: move MCP_GP0 via (151.1,126.5) + local UP jog east, else add U501 +0.35 mm shift (within owner's 'either, smallest change').
  • 2026-11-02: USBHub2 ROUTING COMPLETE 0ef32f1 (pushed), verified by me: DRC 0/0, ERC 0, parity 411/411, audit 0 FAIL, prot 0 (USB_UP baseline updated: 49.973/49.972, skew 0, 2/2 vias), warnings no worse than a523682. U501 moved +0.45 mm east for U501.3 GND via. Margins: UP/MCP_GP0 In2 voids ~0.56 vs 0.55. Draft PRs: EmbeddedEra/Switched_USB_Hub#1 (hub2), #2 (hub3); both merge cleanly into main together. Not merged: fab blockers in Open still apply.