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BLE_Module

Own small BLE module like the Ebyte E73: nRF54L15-QFAA (alternate nRF54L05-QFAA, same pinout), chip antenna, castellated. Repo EmbeddedEra/BLE_Module (local ~/Documents/GitHub/BLE_Module, not yet on GitHub), board hardware/BLE54_Module. Library parts on KiCad branch ble54-module-parts (worktree ~/Documents/GitHub/KiCad-ble54). Related: Garage_Door_Adapter (GDA_Sensor uses the E73 today; first user), kicad-autorouter (layout test board).

Handoff (2026-10-31) — read this first

  • State: 12 x 16 mm LGA module (owner 2026-10-31), every part hand-placed in pcb_src.py, BLE_Module ce47769 (pushed: github.com/EmbeddedEra/BLE_Module, private). J401 = make_lga_footprint.py: 35 bottom pads at 1.0 mm (0.5 x 0.9, 0.3 mm from edge) + 5 centre GND 1.5 mm, CCW: 1-14 left, 15-23 bottom, 24-31 right, 32-35 top, 36-40 centre; none in the antenna corner. Antenna corner per Johanson 36S0021A rev 4.0 = 6.5 x 6.5 mm top right (x 105.5..112, y 100..106.5), AE301 horizontal at (108.45, 102.5), feed at x 107.0. U201 rot 90 at (106.3, 111.0). RF column x 105.1 (L301 106.4 .. R301 101.9), shunts at x 103.95. Default clearance 0.15, board min 0.15 (.kicad_pro). DRC: 0 clearance/edge/courtyard; left = 78 unconnected, 4 isolated pour islands, 6 starved thermals, 36 silk warnings (refs on F.Fab only, board too small).
  • Next action: routing. GPIO escape vias in the ~1 mm bands round U201 (top-right pins 25-30 have only 1.15 mm under the antenna corner); C301 ground only to VSS_PA pin 32 on top, C302 ground to bottom layer; 50 ohm feed R301 -> AE301; GND stitching; add an antenna keep-out rule area on all layers (the placer drops zones on a fresh build, so add it after --keep-placed or teach the placer polygons/rule areas). Then fix the 18 schematic text overlaps (see Open).
  • Library: PR #7 merged 2026-10-31 (6ab9dc9, owner asked); ~/Documents/GitHub/KiCad back on master.
  • Env (Mac): export PATH=/Applications/KiCad/KiCad.app/Contents/MacOS:$PATH KICAD_LIB_REPO=~/Documents/GitHub/KiCad EMBEDDEDERA_DIR=~/Documents/GitHub/KiCad EMBEDDEDERA_FOOTPRINT_DIR=~/Documents/GitHub/KiCad/footprints KICAD_LIB=~/Documents/GitHub/KiCad; placer with KiCad's python /Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/Current/bin/python3 ~/Documents/GitHub/KiCad/scripting/pcb/pcb_from_netlist.py BLE54_Module.kicad_pcb <net> pcb_place.json (netlist: kicad-cli sch export netlist --format kicadsexpr). Page: python3 tools/project_page/build.py <out>, publish to https://claude.ai/artifact/LhLv4i1xG97mMtuRX4n6US (v8) with the same file list. zsh: quote "${c}:path" in git show ($c:h is a zsh modifier).

Open

  • Merge EmbeddedEra/KiCad#10 (CC2340R52 parts; based on #9) once owner OKs; #9's nRF parts no longer used by this board.
  • Confirm on the nRF54L15 datasheet that WAKE (P0.02) can wake from System OFF (assumed: P0 is the low-power domain).
  • Owner review of the schematic on the project page.
  • ERP IPNs: new library parts + board class P.
  • Routing (see Handoff next action); eeroute for the GPIO fan-out.
  • Library (merged, PR #5): run kicad-check on server, add 3D models (QFN-48 EP4.6, Crystal 2012), LCSC numbers, confirm manufacturer spellings (Nordic Semiconductor ASA?).
  • Bring-up: VNA tuning of C304/C305, Nordic DTM, PPK2 sleep current.

Decisions

  • Pad map follows the CC2340 pins (owner 2026-10-31): left pads 3-14 = UART_TX, UART_RX, WAKE, I2C_SDA, SWDIO, SWDCLK, AIN0, AIN1, I2C_SCL, NRESET, LED, IO1; pad 19 IO2; VDD 2 and 17; rest GND. Reason: routing failed on 9 nets crossing the board. No Freerouting (owner declined the download). 2026-10-31.
  • MCU = TI CC2340R52E0RGER, QFN24 4x4 (owner 2026-10-31, replaces nRF54L15): lowest sleep from primary datasheets (SWRS272F: 0.165 uA shutdown/pin wake, 0.71 uA standby RTC+full RAM on internal LFOSC, RX 5.3 / TX 0 dBm 5.1 mA, DCDC 10 uH + 10 uF on VDDR). Compared vs nRF54L15 (0.7 / 3.5 uA LFRC 256 KB, 3.4/4.8 mA) and EFR32BG22 (0.17 / 1.75 uA, 3.6/4.1 mA); Asian parts (RTL8762E, ESP8684, CH592, Telink, Phyplus) had no verified primary data or worse numbers. Follow TI's LP-EM-CC2340R5-RGE-4x4 reference design. Pin plan: SWD DIO16/17, UART TX/RX DIO13/DIO12, I2C SDA/SCL DIO8/DIO24, AIN0/1 DIO20_A11/DIO21_A10, WAKE DIO11, LED DIO3, spare DIO4 (pad 19) + DIO6_A1 (pad 3); no SPI (needs 4 more pins). 2026-10-31.
  • No SPI (owner 2026-10-31): pads 3/5/7/8 and P1.09/P1.11/P1.13/P1.14 no-connect (footprint/symbol unchanged, 30 pads); decaps may sit up to ~2 mm from their pins. Reason: round 5 found the 1.9 mm left band can't hold L101, C102-C104 and six SPI/I2C escapes. Supersedes the SPI part of 'Fewer pads'. 2026-10-31.
  • 0201 decaps (Nordic's sizes; 10u stays 0402) + 1612 32 MHz crystal (owner 2026-10-31): round 4 could not fit the 0402 caps at their pins or the SPI/I2C escape past the 2016 crystal on 12x16. 2026-10-31.
  • Only necessary parts on this board (owner 2026-10-31). Checked against Nordic's config-1 BOM: every part is Nordic's except the antenna tuning pi-network R301/C304/C305, which the owner keeps for VNA tuning. Sizes: changed to Nordic's 0201 later the same day (see next line). 2026-10-31.
  • No 32.768 kHz crystal (owner 2026-10-31): internal LFRC (CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC); a little more sleep current; frees the left exit for SPI/I2C. Supersedes 'crystal fitted' below. 2026-10-31.
  • Fewer pads (owner 2026-10-31): 30 LGA pads, no bottom row. Host gets VDD, GND, SWD + NRESET, UART P0.00/P0.01, WAKE P0.02, spare P0.03, LED P2.07, I2C SDA/SCL P1.10/P1.12, SPI CS/SCK/MOSI/MISO P1.09/P1.11/P1.13/P1.14, AIN0/1 P1.04/P1.05; other GPIOs NC. Reason: the first routing pass found no via room for the bottom pad row and the 29-GPIO pin-out. 2026-10-31.
  • 12 x 16 mm LGA, all 29 GPIO (owner 2026-10-31). 12 x 12 cannot fit: Johanson's antenna needs a 6.5 x 6.5 mm copper-free corner and the GPIOs need ~1 mm escape bands. Supersedes 12 x 12 and 20 x 20. 2026-10-31.
  • (superseded 2026-10-31) 12 x 12 mm LGA; stencil/reflow only and the whole-10 mm outline override still stand. 2026-10-30.
  • nRF54L15 on schematic, nRF54L05 as ERP BOM alternate; Nordic config 1 (DC/DC, no NFC) as published; Johanson 2450AT18A100 chip antenna with pi-match; 32.768 kHz crystal fitted; 40 pads (29 GPIO); JLCPCB rule file. 2026-10-30.

Log

  • 2026-10-31: CC2340 routing paused, waiting on owner. 17d7624 (local): centre GND pads 27/29 moved right + shrunk to 1.2 mm; 0 DRC errors, 29 unconnected with the no-via-in-LGA-pad rule (earlier 'nearly routed' runs used 14 vias inside LGA pads). Blocker: no via room between U201 west pins (x 101.4-102.0) and left LGA pads (x <= 101.2) for 12 signals. Options put to owner: filled+capped via-in-pad (stays 12x16, paid at JLC 4L), widen to 13x16, or hand lane plan.
  • 2026-10-31: CC2340 board: placement 11e3b43 (0 DRC errors), router 9 nets short (9eb9bfd); pads re-mapped eb7c28f; helper routing again.
  • 2026-10-31: CC2340R52 parts in EmbeddedEra/KiCad#10 (TI SWRR189A RGE reference design; zero-stock Murata MLCCs and TZ3908 crystal swapped for in-stock equivalents, crystal Kyocera CX2016DB48000C0FPLC1 ESR 30 R max, CL 7 pF). Schematic 8b9a4b8: 21 parts, netlist = source, pad->pin 0 mismatches, 0 overlaps, ERC lib-table only. Board place/route helper running.
  • 2026-10-31: chip comparison (TI/SiLabs/Nordic from their datasheets; Asian vendors no primary data) -> owner picked CC2340R52. Library parts + TI reference circuit delegated to engineering agent (new KiCad PR off ble54-0201-1612-parts). nRF54L15 board work (70fa2b9) is superseded.
  • 2026-10-31: owner stopped the routing work after round 6 (22 unconnected; attempt in session scratchpad round6_attempt/, Y201 0.1 mm rule proven there). State: BLE_Module 70fa2b9 local (nothing after ce47769 pushed), KiCad checkout on ble54-0201-1612-parts, KiCad#9 open. Open options when resumed: widen to 13x16, via-in-pad, or Freerouting instead of pcb_autoroute.py.
  • 2026-10-31: round 5 blocked (left band, 19 unconnected; attempt in session scratchpad round5_attempt/). Owner: drop SPI -> 70fa2b9 (netlist = source, tidy 0 overlaps). Round 6 helper running.
  • 2026-10-31: owner accepted Abracon ABM12W-32.0000MHZ-8-D1X-T3 (1612, 8 pF, +/-30 ppm) although its worst-case ESR 80 R / C0 2 pF sits ~10 R over Nordic's ESR-C0 curve (typ <60 R passes): check 32 MHz start-up on first boards. Parts in EmbeddedEra/KiCad#9 (open, unmerged; local checkout on its branch). Footprint = Abracon land pattern exactly (0.12 mm pad gap; board rule exception for Y201 only, JLC 4L min 0.09). Schematic 5c262c9 (netlist = source, 0 overlaps). Routing round 5 running.
  • 2026-10-31: owner: 0201 decaps (Nordic's sizes: 100n, 2.2u, 10n, 2.2n, 120R bead; 10u stays 0402) + 1612 32 MHz crystal instead of 2016, because round 4 (72d83aa, DRC 0 errors / 14 unconnected, C104/C203 ~8 mm from pins 43/36) ran out of room in the 12x16 bands. Library parts delegated to engineering agent (KiCad PR); then sch_src.py swap + routing round 5.
  • 2026-10-31: routing rounds 2-3 (helpers): placement + critical copper locked, grid router pcb_autoroute.py; f5c63ab = 0 DRC errors, 16 unconnected, C104/C203 ~8 mm from pins (unacceptable). Eeroute timed out on plex (numpy missing). Owner: drop Y202 -> bf244ee (schematic checked). Round 4 helper re-places and finishes.
  • 2026-10-31: owner: merge -> EmbeddedEra/KiCad#8 merged (cebd328); KiCad checkout back on master.
  • 2026-10-31: first routing pass stopped (af5186b: antenna keep-out rule area via pcb_routes.py): no via room at the bottom/right pad rows. Owner: fewer pads. 8723b0c = 30 pads by function, pad-to-pin check 0 mismatches, tidy 0 overlaps (old 18-overlap item closed), ERC clean. KiCad PR #8 opened (merge refused by review check). Round 2 re-place + route handed to the helper.
  • 2026-10-31: owner: merge KiCad PR #7 (done, 6ab9dc9) and route the board; routing handed to a helper (eeroute on plex + scripted RF routes).
  • 2026-10-31: owner: create the repo and push -> EmbeddedEra/BLE_Module (private), main pushed at ce47769.
  • 2026-10-31: Johanson clearance check (6.5 x 6.5 corner) ruled out 12 x 12; I first said 12 x 14 from part outlines only, then corrected to 12 x 16 once escape vias counted; owner picked 12 x 16. LGA footprint, pad map, hand placement, 0.15 clearance; DRC clean of placement errors (ce47769). Page v8.
  • 2026-10-30: owner: 20 x 20 mm, 1.0 mm pitch. 3D models generated (KiCad lib PR #7, merge blocked by permission check). Placer fix for edge footprints. First auto placement: 27 footprints, DRC not clean (see Handoff). Page v7 with renders.
  • 2026-10-30: Power sheet drawn as chains like RF (8768bc7). Owner: merge the KiCad work -> merged EmbeddedEra/KiCad#5 (5f343c0, BLE parts + FB bead resize + sch_tidy FB two-pin), #6 (e120399, template title block 006), Project_Template#2 (3624c44, was draft; title block 006 + CI). No CI ran (Actions billing; kicad-check server-only). BLE54 builds against master (64965df). Page v6.
  • 2026-10-30: title block 006 (owner: latest) on BLE54 (53ae74a). Library PR #6, Project_Template PR #2 updated.
  • 2026-10-30: title block 003 -> 005 (BLE_Module 6039cbf): Project_Template's board-1 still ships 003 (fix = open PR EmbeddedEra/Project_Template#2); sch_gen write_project never sets the worksheet, so new boards from the template inherit it. 006 (KiCad 697547b) still waiting on the owner's 005-vs-006 pick (see project-template note). Page v4.
  • 2026-10-30: owner (supersedes ESP32-style line below): chip symbols follow the vendor's reference schematic exactly; nRF54L15 now Nordic's 4 units (A power/RF/debug, B/C/D = P0/P1/P2), KiCad PR #5 2c9c666; board be3262b. Caught and fixed a P1 pin-mapping slip on the way (pad check: 29/29 GPIO match). Page v3.
  • 2026-10-30: (superseded) owner: MCU symbols in ESP32 style (one VDD pin top, one VSS bottom, others stacked hidden; ports on the sides) and RF chains drawn as wires, not net labels. nRF54L15 symbol redone (KiCad PR #5, e0311e8, pushed); RF sheet wired; reset filter moved beside pin 30 (BLE_Module a564928, local). Netlist = source, 0 overlaps, ERC 0 electrical. Page v2 published.
  • 2026-10-30: schematic generated (BLE_Module accbaec, local only): 4 sheets, netlist = source, tidy 0 overlaps, ERC 0 electrical (library-table warnings = Mac env, GDA shows the same). Library PR EmbeddedEra/KiCad#5 (ble54-module-parts 7c3144a): kicad-check not run (server only); no 3D model yet for QFN-48 EP4.6 and Crystal 2012; LCSC only for C101/L101. Project page https://claude.ai/artifact/LhLv4i1xG97mMtuRX4n6US ($8.34/module qty 1; 100n 0402 YAGEO has no quote).
  • 2026-10-30: started. Pinout, reference circuit (config 1 QFN48) and package (EP 4.6x4.6) read from Nordic's HTML datasheet (PDF links are bot-blocked; browser works). Repo built locally from Project_Template; sch_src.py written; library parts delegated to engineering agent.