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ATtiny3217 and UPDI: things that bit us on Cricket 008

Learned 2026-09-25 to 2026-09-28 on the Cricket 008 bench. Related: cricket-product · updi-front-end

  • Every UPDI disconnect resets the chip. avrdude puts the part in reset to talk to it and releases it on exit, so each read re-runs whatever image is on the board (a read after a test image adds a boot). Never poll a running test with repeated avrdude reads: wait once, read once.
  • The bench SerialUPDI adapter drives the VCC/+BATT pin at about 5.2 V (measured with the chip's own ADC). Attached together with a LiPo it forces 5 V into the cell. Cell out before the programmer goes on.
  • 20 MHz needs 4.5 V. On a LiPo (3.0 to 4.2 V) the CPU is limited to 10 MHz: run the 20 MHz oscillator through the /2 prescaler. The oscillator choice is a fuse, OSCCFG (fuse2): 0x02 = 20 MHz. The datasheet default is 16 MHz, so a virgin chip has to be fixed (not yet seen on a virgin chip; the bench board already read 0x02).
  • EEPROM survives programming only if EESAVE is set. SYSCFG0 (fuse5) 0xF6 has EESAVE clear, so avrdude's chip erase before a flash write also erases EEPROM. Cricket relies on that: an erased EEPROM byte 255 means "ship asleep".
  • A chip in power-down can still be programmed over UPDI, and USERROW reads work while it sleeps. USERROW survives a chip erase unless blanked explicitly (userrow:w: with 64 bytes of 0xFF).
  • Rail capacitors hold VCC above the power-on-reset level for a long time when the chip sleeps at about 1 µA, so replugging the battery does not reset it. Short the caps to GND first.
  • avrdude 8.1 memory names for the t3217: signature, sernum (10 bytes, unique per chip), fuse0 to fuse8, userrow (64 B), eeprom (256 B), flash.